Periodic register saturation in innermost loops
نویسندگان
چکیده
منابع مشابه
Periodic register saturation in innermost loops
This article treats register constraints in high performance embedded VLIW computing, aiming to decouple register constraints from instruction scheduling. It extends the register saturation (RS) concept to periodic instruction schedules, i.e., software pipelining (SWP). We formally study an approach which consists in computing the exact upper-bound of the register need for all the valid SWP sch...
متن کاملDeciding Innermost Loops
We present the first method to disprove innermost termination of term rewrite systems automatically. To this end, we first develop a suitable notion of an innermost loop. Second, we show how to detect innermost loops: One can start with any technique amenable to find loops. Then our novel procedure can be applied to decide whether a given loop is an innermost loop. We implemented and successful...
متن کاملRegister Saturation in Superscalar and VLIW Codes
The registers constraints can be taken into account during the scheduling phase of an acyclic data dependence graph (DAG) : any schedule must minimize the register requirement. In this work, we mathematically study and extend the approach which consists of computing the exact upper-bound of the register need for all the valid schedules, independently of the functional unit constraints. A previo...
متن کاملCoherency saturation in periodic structures with randomization
We study the effect of coherency saturation in spatially or temporally periodical structures with randomization, applicable to a very broad class of systems. We derive a simple analytical formula in the case of uncorrelated deviations of periods with Gaussian probability distribution. Using Monte Carlo simulations, we also demonstrate that many other distributions show statistical properties th...
متن کاملAddress register allocation for arrays in loops of embedded programs
Efficient address register allocation has been shown to be a central problem in code generation for processors with restricted addressing modes. This paper extends previous work on Global Array Reference Allocation (GARA), the problem of allocating address registers to array references in loops. It describes two heuristics to the problem, presenting experimental data to support them. In additio...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Parallel Computing
سال: 2009
ISSN: 0167-8191
DOI: 10.1016/j.parco.2008.12.001